It is a
command given to a computer to perform specific operation on given data. The
entire group of instruction called the instruction set. In 8085, instruction
set can be classified into 5 different groups.
i.>
Data
transfer group
ii.>
Arithmetic
group
iii.>
Logical
group
iv.>
Branching
group
v.>
Miscellaneous
Data transfer group: These
instruction which are used to transfer a data from one register to another or
register to memory or vice versa. E.g. MOV, MVI, LDA etc.
a)
MOV Rd, Rs
-
1 byte
instruction
-
It
copies data from source register too destination register
-
Rd and Rs
may be A,B,C,D,E,H,L
-
E.g. MOV
A,B;(A<-B)
b)
MVI R,
8-bit data(move immediate
instruction)
-
2 byte
instruction
-
Loads
the 8-bit of data into the specified register
-
R may be A,
B, C, D…….etc.
-
E.g. MVI
C,20H;C<-20H
c)
MOV M,R(move to memory from register)
-
Moves
the content of the specified register to memory
-
Here the
memory is the location specified by the content of HL pair register
-
E.g. MOV M,
A;([HL]<-A)
d)
MOV R, M
-
1 byte instruction
-
Moves
the content of the specified memory to register
e)
MVI M,8-bit
data(move 8-bit data immediate
to memory)
-
2 bytes
data instruction
-
Loads
the 8-bit data on the memory location where address is specified by HL pair
register.
-
E.g. MVI H,
32H
MVI L, 00H
MVI M, 20H
f)
LXI Rp,
16-bit data(load register pair
immediate)
-
3 bytes
instruction
-
Loads
the 16-bits data immediately to the pair register
-
Rp may be
B,D,H
-
E.g. LXI B,
2000H
-
Here, 1st byte=LXI B(op-code)
2nd byte=20H (upper byte operand)
3rd byte= (lower byte operand)
g)
LDA 16-bits address (load accumulators direct)
-
3 bytes
instruction
-
Loads
the accumulator with the content of memory location whose address is specified
by 16-bit
-
E.g. LDA
5000H;A<-[5000H]
h)
STA 16 bit
address(store accumulator content)
-
3 bytes
instruction
-
Stores
the content f accumulator to the specified memory location
-
E.g. STA
5000H;[5000H]<-A
i)
LDAX Rp (load accumulator indirect)
-
1 byte
instruction
-
Loads
an accumulator from the memory location indirectly specified by pair register.
-
E.g. MVI B,
20H;B<-20H
MVI C, 40H;C<-40H
LDAX B;A<-[2040H]
j)
STAX Rp (here accumulator content
indirectly)
-
1 Byte
instruction
-
Stores
accumulator content to the memory location indirectly specified by pair
register
-
E.g. MVI D,
30H; D<-30H
MVI E, 00H; E<-00H
STAX D;[3000H]<-A
k)
IN 8 bit
address
-
1 byte
instruction
-
Reads data
from the input port specified by the second byte and loads into accumulator
-
E.g. IN
40H; A<-[40H]
l)
OUT 8 bit
address
-
2 byte
instruction
-
Copies the
content of accumulator to the output port specified in the 2nd byte.
-
e.g. OUT
40H,[40H]<-A
m) LHLD 16 bit address(load HL register directly)
-
3 bytes
instruction
-
Loads the
content of memory location to L register next higher address content into H register
-
E.g. LXI
H,9500H; H<-95H,L<-00H
MVI M,3AH;[HL][9500H]<-3A
MVI M,20H;L<-01H
MVI M,20H;[HL][9500H]<-20H
LHLD 9500H;
n)
SHLD 16 bit
address(store HL register directly)
-
3 bytes
instruction
-
Stores
content of L register into specified location and content of H register into
next higher memory location.
-
E.g. LXI H,
9500H; H<-95H,L<-00H
SHLD 8000H
o)
XCHG(exchange)
-
1 byte
instruction exchange DE pair register with HL pair register.
-
E.g. LXI H,
9500H;
LXI D, 1080H;
XCHG; H<-10H, D<-95H, L<-80H, E<-00H
Arithmetic Group Instruction: The 8085 microprocessor performs various arithmetic
operations such as addition, subtraction, increment and decrement. These
arithmetic operations have the following mnemonics.
i.
ADD R/M
-
1-byte
instruction
-
Adds the
content of register/memory to the content of accumulator and stores the result
in accumulator.
-
E.g. ADD B ADD M
A<-A+B A<-A+[HL]
ii.
ADI 8-bit
data
-
2-byte
instruction
-
Adds the
8-bit immediate data with the content of accumulator and stores in accumulator
-
E.g. ADI
90H; A<-A+90H
iii.
SUB R/M
-
1-byte
instruction
-
Subtract
the content of register or memory from the content of accumulator and stores
the result in accumulator
-
E.g. SUB B; A<-A-B
SUB M; A<-A-[HL]
iv.
SUI 8 bit
data
-
2-byte
instruction
-
Subtract the
8-bit data immediately from the content on accumulator and stores result in
accumulator
-
E.g. SUI
30H; A<-A-30H
v.
INR R/M,
DCR R/M
-
1-byte
instruction
-
Increment
and decrement the content of register or memory by one respectively. (Does not
affects flag)
-
E.g. INR B;
B<-B+1
DCR M; M<-M-1
vi.
INX Rp/DCX
-
1-byte
instruction
-
Increment
or decrement the content of pair by one
-
Acts as
16-bit counter mode from the content of Rp
-
No flags
affected
-
E.g. INX B;
BC<-[BC]+1
DCX D; DE[DE]-1
vii.
ADC R/M
(addition with carry)/ACI 8 bit data (immediate addition with carry)
-
1-byte
instruction (2-byte instruction)
-
Adds the
content of register or memory whatever used suitable with previous carry
-
E.g. ADC B;
A<-A+B+CY
ACI 70H
viii.
SBB R/M
(subtract with borrow/SBI 8 bit data(immediate, subtract with borrow)
-
1 byte/
2-byte
-
Subtracts
the content of register or memory or 8 bit data from the content of accumulator
with previous borrow
-
E.g. SBB M;
A<-A-M-borrow
SBB 70H; A<-70H-borrow
ix.
DAD Rp
(Double Addition)
-
1 byte
instruction
-
Adds
register pair with HL pair and stores the 16 bit result in HL pair
-
E.g. LXI H,
7320H
LXI B, 4220H
DAD B, [HL] <-[HL]+[BC]
<-7320+4220=
x.
DAA
(Decimal adjustment accumulator)
-
1 byte
-
Used only
after addition
-
The content
of accumulator is changed from the binary to 4-bit BCD
-
E.g. MVI A,
78H
MVI B, 42H
ADD B
DAA
Logical Group: A microprocessor is basically a programmable
logic chip which can perform all the logic function of the hardwired logic
through it instruction set. The 8085 instruction sets the 8085 instruction set
includes such logic functions as AND, OR and NOT. The following features hold
true for all logic instruction.
a.
The
instruction implicitly assumes that the accumulator is one of the operands.
b.
All
instruction reset (0) carry flag except the instruction complement (CMA)
c.
They modify
Z, P, and S according to the data condition of the result.
d.
Place the
result in accumulator
The logical
operations have the following instructions.
i.
ANA R/M
·
Logically
AND the content of register or memory with the content of accumulator.
·
CY flag is
reset and AC set
·
E.g. ANA B
; A<-A&&B
ii.
8 bit data
ANI
·
Logically
AND 8-bit data immediately with the content of accumulator
·
E.g. ANI
72H; A&&72H
iii.
ORA R/M
·
Logically
OR the content of register or memory with the content of accumulator
·
CY flag
reset and AC reset.
·
E.g. ORA B;
A||B
iv.
ORI 8 bit
data
·
Logically
OR the 8 bit data immediately with the content of accumulator.
·
E.g. ORI
72H; A||72H
v.
XRA R/M
·
Logically,
X-OR the content of register or memory with the content of accumulator.
·
CY flag is
reset and AC reset the other as per result
vi.
XRI 8 bit
data
·
Logically,
X-OR 8 bit data immediately with the content of accumulator.
·
E.g. XRI
72H; A<-Ax||72H
vii.
CMA
·
Complement
the content of accumulator
·
No flags
affected
·
E.g. CMA ; A<-A|
viii.
STC
·
Set carry
flag
ix.
CMC
·
Complement
carry flag
x.
CMP R/M
CPI 8-bit data
·
Compares
the content of register/memory or 8 bit immediate data with the content of
accumulator.
|
|
CY
|
Z
|
|
|
A < R/M or 8-bit data
|
1
|
0
|
A-R<0
|
|
A > R/M or 8-bit data
|
0
|
0
|
A-R>0
|
|
A = R/M or 8-bit data
|
0
|
1
|
A-R=0
|
Logically Rotate Instructions
i.
RLC (Rotate
Accumulator Left)
ii.
RAL (Rotate
Accumulator Left Through Carry)
iii.
RRC (Rotate
Accumulator Right without Carry)
iv.
RAR (Rotate
Accumulator Right Through Carry)
Note: The rotate instructions are primarily used in arithmetic multiply
and divide for serial data transfer. E.g. if accumulator contains 08H 00001000,
by rotating 08H to right accumulator A becomes (00000100). It is equal to
dividing by 2. However, this procedure is invalid logic 1 is rotated D7 to D0
or vice versa.
Example: 80H -> 10000000 (left)
01H -> 00000001 (right) invalid
Branching Group Instruction
The branching instruction instructs
the processor to go to a different memory location and the microprocessor
continues excluding machine code from the new location.
The
branching instructions are the most powerful instructions because they allow
the microprocessor to change the sequence of program either unconditionally or
under certain test condition. The branching instructions are divided into
following 3 groups:
a.
JUMP
instruction
b.
CALL and
RET instruction
c.
RESTART
instruction
The jump instruction specifies the
memory location explicitly. They are 3 bytes instruction.
Jump instruction categories into
unconditional and conditional.
1.
Unconditional Jump: 8085 includes unconditional JUMP instruction loop without depending any
types of conditions.
JMP 16-bit address
e.g. JMP 4000H
Memory location can also be
specified with a label or name
2. Conditional
Jump: The
conditional JUMP instructions allow the microprocessor to make decision based
on certain condition indicated by the flag. After logical and arithmetic
operations flag are set or reset to reflect condition.
The four flags namely CY, P, Z and
S are used by JUMP instructions.
|
MNEMONICS
|
DESCRIPTIONS
|
|
JC 16 bit address
|
Jump on carry (CY=1)
|
|
JNC 16-bit address
|
Jump on no carry (CY=0)
|
|
JZ 16-bit address
|
Jump on zero (Z=1)
|
|
JNZ 16-bit address
|
Jump on no zero (Z=0)
|
|
JP 16-bit address
|
Jump on plus (S=0)
|
|
JM 16-bit address
|
Jump on minus (S=1)
|
|
JPE 16-bit address
|
Jump on parity even (P=1)
|
|
JPO 16-bit address
|
Jump on parity odd (P=0)
|
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